This invention relates to DC link variable speed constant frequency (VSCF) power systems having at least two parallel connected channels, and more particularly, to a method and circuit for protecting such systems by sensing unbalanced real current flow and producing a selective trip signal when the unbalanced real current flow reaches a predetermined level.
AC electric power systems are usually connected in parallel to increase total system rating or, in certain cases such as airborne power systems, to increase reliability. In order to further improve reliability and to maximize efficiency, it is generally desired that the total system load be divided equally among the paralleled generators. Parallel connected DC link variable speed constant frequency power sources constitute a clock based system in which a single digital clock signal is delivered to all channels whether or not they are connected to the parallel load bus. The clock signal is generally a 400 hertz squarewave. The angle between each channel Thevenin voltage and the clock signal represents an angle error. The angle error closes the feedback loop to control the channel's Thevenin angle. Synchronism is thus assured in a phase-locked loop manner. A commonly assigned patent application entitled "DC Link Variable Speed Constant Frequency Power Source Paralleling Controls", Ser. No. 938,661, and filed on the same day as the present application discloses a control system for such a power system. That application, which is hereby incorporated by reference for background material, discloses a system having a real load division loop which adds an input to a phase-locked loop clock circuit in a manner such that the phase angle is controlled to offset any real load unbalance.
Although the frequency reference signal is used as the vehicle for obtaining the desired phase angle change, the control system does not alter the steady state frequency of the output. Unlike parallel connected constant speed generators, the VSCF system does not have a frequency droop with real load errors. It has an angle droop with real load errors. VSCF systems do not exhibit frequency droop with any load conditions because the system frequency is determined totally independent of the generator speed and torque.
To this end, it is impossible to bias the VSCF over frequency/under frequency (OF/UF) protection circuits with the real load division error to get selective tripping of the parallel channels. A protection circuit which can selectively trip parallel connected DC link VSCF channels in the event of excessive real current unbalance, is therefore required.